• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    The invention relates to a device comprising: a chip (1) mounted on an interposer (3); an electrically insulating layer (27) coating the upper face (7) of the interposer around the chip; first metal lines (31) resting on the upper face of the interposer and being disposed between conductive elements connecting to the chip, at least one end of each first line being disposed beyond the projection of the chip on the interposer; and thermally conductive vias (35) connecting said at least one end (34) to a radiator (29) resting on the upper face of the device.
    公开号:FR3018953A1
    申请号:FR1452280
    申请日:2014-03-19
    公开日:2015-09-25
    发明作者:Pierre Bar；Alisee Taluy；Olga Kokshagina
    申请人:STMicroelectronics SA；STMicroelectronics Crolles 2 SAS；
    IPC主号:
    专利说明:

    [0001] B13107UK-12-GR3C0-0471EN01 1 INTEGRATED CIRCUIT CHIP MOUNTED ON AN INTERPOSER Field This application relates to a mounting of at least one integrated circuit chip on an interposer and a method of manufacturing such an arrangement.
    [0002] DISCUSSION OF THE PRIOR ART In a so-called three-dimensional integrated circuit assembly, at least one integrated circuit chip is mounted on an intermediate plate commonly called an interposer. The interposer provides the connection between the chip or chips and a device support disposed on the side of the interposer opposite to that on which the chips are mounted. FIGS. 1A and 1B are cross-sectional views illustrating such a three-dimensional arrangement of a chip 1 and an interposer 3, respectively before and after the chip has been mounted on the interposer. Figure LA is an exploded sectional view showing the chip 1 above the interposer 3. The face of the chip on the side of which are formed integrated circuits, or active face 5, is opposite the upper face 7 of the interposer. The active face 5 carries an interconnection network 8 (not shown in detail) for connecting terminals of the chip together and to connection elements 9, such as metal micro-pillars. , carried by the active face 5. The upper face 7 of the interposer comprises connecting elements 13 similar to the connection elements 9 5 of the chip, the elements 9 and 13 being opposite each other. Each connection element 13 is carried by a pad 15 formed on and in a passivation layer 17, the pads 15 being electrically bonded to the last metal level of an interconnection network 19. The interposer comprises through vias 10 21 each of which connects a pad (not shown) of the lower surface of the interposer to one of the pads 15 via the interconnection network 19. In Figure 1B, the chip 1 is mounted on the interposer 3. Each element 9 of the chip is connected to a connecting element 13 of the interposer by a solder 23. An electrically insulating material 25, for example a resin injected after soldering, fills the space between the active face 5 of the chip and the upper face 7 of the interposer, around the connection elements 9 and 13. An electrically insulating layer 27, for example a resin, covers the upper face 7 of the interposer around the chip. A radiator 29 rests on the upper face of the assembly. In this arrangement, the interposer 3 makes it possible to adapt the tight pitch of the connection elements 13 to the looser pitch of the connection elements (not shown) on the side of the lower face of the interposer. On the side of the lower face of the interposer, the pitch of the connection elements corresponds to the possible pitch of the connections of a support on which the assembly will be mounted. This support may be a final support such as a printed circuit board. The support may also be an intermediate support constituting a second interposer. In operation, the components of chip 1 produce heat. The thermal energy produced is partly diffused to the radiator 29 through the thickness of the chip. Because of the limited thermal conductivity of the chip B 1, the thermal energy is not properly discharged to the radiator 29. The temperature of certain regions of the chip and the assembly can then increase until it deteriorates.
    [0003] There is therefore a need to improve thermal energy transfer in a three-dimensional arrangement including an integrated circuit chip mounted on an interposer to reduce temperature in the hottest regions of the assembly.
    [0004] SUMMARY Thus, an embodiment provides a device comprising: a chip mounted on an interposer; an electrically insulating layer coating the upper face of the interposer around the chip; first metal lines resting on the upper face of the interposer and being disposed between conductive elements connecting to the chip, at least one end of each first line being disposed beyond the projection of the chip on the interposer; and thermally conductive vias connecting said at least one end to a radiator resting on the upper face of the device. According to one embodiment, the conductive connection elements to the chip and the metal lines are in the same first material and have the same thickness.
    [0005] According to one embodiment, the width of each of the first lines is less than the width of said at least one corresponding end. According to one embodiment, the first material is copper.
    [0006] According to one embodiment, each conductive connection element to the chip is bonded by a solder to a conductive connecting element to the corresponding interposer formed on the chip. According to one embodiment, second metal lines rest on the chip between said elements of the connection to the interposer, these second lines being thermally bonded to the corresponding first lines by a solder. According to one embodiment, the connection elements to the interposer and the second metal lines are in the same second material and have the same thickness. According to one embodiment, an electrically insulating material fills the free space between the chip and the interposer. According to one embodiment, the second material is copper. One embodiment provides a method of manufacturing a chip assembly on an interposer, the method comprising the steps of: forming pads on the upper face of the interposer; deposit a polarization metal layer on the upper face of the interposer; depositing a masking layer on the polarization layer; etching the masking layer up to the polarization layer to form openings facing the pads and to form trenches; dip the interposer into an electrolytic bath comprising metal ions and apply a voltage between the bias layer and an electrode plunged into the electrolytic bath to grow first metal lines in the trenches and chip connection elements in the electrolytic bath. openings; Removing the interposer from the electrolytic bath; remove the masking layer; etching the polarization layer, the first metal lines and the connection elements to the chip serving as an etching mask; B13107EN - 12-GR3C0-0471EN01 mounting the chip on the upper face of the interposer by brazing the connection elements to the chip on the connection elements to the interposer worn by the active face of the chip; Filling the free space between the chip and the interposer with an electrically insulating material; depositing an insulating layer on said upper face, the insulating layer flush with the face of the chip opposite to the active face; and forming thermally conductive vias through the insulating layer, these vias being bonded to the ends of the first lines. According to one embodiment, there are provided second metal lines carried by the active face of the chip, each second line being thermally bonded to the corresponding first line by a solder made at the step of mounting the chip on the interposer. According to one embodiment, said trenches comprise flared ends.
    [0007] According to one embodiment, the method further comprises a step of polishing the upper face of the assembly and a step of mounting a radiator on the upper face of the assembly. According to one embodiment, the metal ions of the electrolytic bath are copper ions. BRIEF DESCRIPTION OF THE DRAWINGS These features and advantages, as well as others, will be set forth in detail in the following description of particular embodiments in a non-limiting manner with reference to the accompanying figures, in which: FIGS. previously, are schematic sectional views of a chip and an interposer before and after mounting the chip on the interposer; FIGS. 2A, 2B and 2C are schematic sectional views of an embodiment of a chip assembly on an interposer; Figures 3A-3B and 4A-AB are schematic views illustrating steps of manufacturing a contact pad; and Figs. 5A-5C and 6B illustrate steps of making an embodiment of mounting a chip on an interposer. For the sake of clarity, the same elements have been designated with the same references in the various figures and the various figures are not drawn to scale. DETAILED DESCRIPTION FIGS. 2A, 2B and 2C schematically show an embodiment of an assembly of a chip 1 on an interposer 3, the interposer constituting part of a silicon wafer in which several interposers are formed. FIGS. 2A and 2C are cross-sectional views of FIG. 2B respectively along the AZ and CC sectional planes, FIG. 2B being a top view of FIGS. 2A and 2C along the BB plane. The assembly comprises the same elements as the assembly of FIG. 1B designated by the same references, namely: a chip 1 mounted on an interposer 3, each of the connection elements 13 of the interposer being electrically connected by a solder 23, for example, an alloy of tin and silver, to a connection element 9 of the chip; an electrically insulating material disposed between the interposer and the chip around the connecting members; an electrically insulating layer 27 coating the interposer around the chip; and a radiator 29, 30 for example a metal sheet, for example copper, resting on the upper face of the assembly. This assembly further comprises metal lines 31 carried by the upper face 7 of the interposer 3 and, preferably, metal lines 32 carried by the active face 35 5 of the chip 1 and brazed to the corresponding lines 31 by a B13107FR - The lines 31 and 32 are arranged between the connection elements 13 and 9, the lines being electrically insulated from the latter by the material 25. The lines 31 and 32 are also electrically isolated from the networks 25. inter-connection 19 and 8 of the interposer and the chip, for example by a passivation layer 17. The lines 31 extend beyond the projection of the chip 1 (in dashed lines in FIG. 2B) and their ends disposed beneath the layer 27 comprise a flare 34. Thermally conductive vias 35 (FIG. 2C) pass through the layer 27 and thermally connect the flares 34, and therefore the lines 31, to the radiator 29. The flares 34 facilitate attempt to connect the vias to the ends of the metal lines. The metal lines 31 and 32, although preferably extending continuously throughout the die 1, may, if necessary, be interrupted, as shown in the central portion of FIG. 2B. In operation, heat is generated by the components formed on the active side 5 side of the chip 1. A large part of the thermal energy thus produced is transferred by the metal lines 31 and 32 to the radiator 29 by Via the vias 35. A thermal bridge was thus made between the face of the chip on the side of the interposer and an external radiator. According to a first variant, the chip-side lines 32 are not made and it is expected that the electrically insulating material 25 is thermally conductive. The thermal energy is then transmitted from the chip 1 to the lines 31 via this material 25. According to a second variant, the lines 32 on the chip side are replaced by a sequence of connection elements similar to the connection elements. 9. In addition, it can be provided that the lines 31 are thermally connected by unrepresented conductive elements to vias 21 passing through the interposer. Part B13107EN - 12-GR3C0-0471EN01 8 thermal energy is then transmitted from the chip 1 to the lower face of the interposer via these vias 21. The chip 1 may be a thinned chip of a surface of 2 mm2 whose thickness is between 80 and 200 pin, for example 100 pin. The thickness of the interposer may be between 70 and 200 pin, for example 80 pin. The insulating material 25 may be a resin, preferably a thermosetting polymer such as an epoxy polymer commonly referred to as Wafer Level Underfill (WLUF) as described in the article "Wafer Level Underfill". Performance of Wafer-Level Underfill with 50 gm pitch interconnections: Comparison with A. Taluy et al. published in 2011 in Electronics Packaging Technology Conference. The insulating layer 27 may be a resin, for example a thermosetting polymer such as an epoxy polymer. The connecting elements 9 and 13 may be micro-pillars with a diameter of between 20 and 30 μm, for example 25 μm, and with a thickness of between 5 and 25 μm, for example 15 μm, the micro-pillars being for example copper. Advantageously, the metal lines 31 are formed at the same time as the connection elements 13, in the same material and in the same thickness. Similarly, the metal lines 32 are formed at the same time as the connection elements 9, of the same material and the same thickness. The width of the lines 31 and 32 may be between 10 and 25 pin, for example 20 pin. The width of a flare 34 may be between 10 and 30 pin, for example 25 pin. The distance between a line and the nearest connection element may be between 10 and 25 pin, for example 20 pin. Figure aA is a top view schematically showing a portion of the upper face of the interposer 3 at a location where it is desired to form a stud 35 15. Figure 3B is a sectional view along the BB plane of the B13107FR Figure aA through the upper part of the interconnection network 19 of the interposer. A portion 40 of the last metal level of the network 19 is disposed under an insulating layer 42, for example a silicon oxide layer. This portion 40 whose dimensions are of the order of those desired for the stud 15 is opposite the location where it is desired to manufacture the stud 15. The portion 40 is electrically connected to the rest of the interconnection network 19 by 44 through apertures 46 have been formed through the insulating layer 42 to the portion 40. These openings 46 are regularly arranged, peripherally or checkered, to join the portion 40 (dashed in Figure aA). In plan view, each opening 46 has the shape of a square. FIGS. 4A and 4B are respectively views from above and in section of the interposer portion 3 of FIGS. AA and 3B after a step of deposition of a metal layer which covers the structure and fills the openings 46. This layer is then etched in a pattern 48 which extends beyond the outer periphery of the openings 46 and which corresponds to a pad 15. As an example, each opening 46 has sides whose length is between 0.5 and 2 lm, for example 1.5 lm. The space between an opening 46 and the nearest opening can be between 1 and 2 pin, for example 1.5 lm. The stud 15 may have the form of a square whose sides have a length of between 25 and 100 pin, for example 25 lm. The pad 15 may be a portion of an aluminum layer whose thickness is between 0.6 and 2 pin, for example 1 lm. FIGS. 5A to 5C illustrate steps of manufacturing connection elements 13 and metal lines 31 on the upper face 7 of the interposer 3. FIG. 5A is a sectional and perspective view showing a portion of the face 7 and the upper part of the interconnection network 19 of the interposer 3. In this figure, pads 15 have been formed at the locations B13107EN-12-GR3C0-0471EN01 10 where it is desired to produce connection elements 13, for example according to the method described above in connection with FIGS. 3A-3B and 4A-4B. Between the pads, the upper face 7 of the interposer is coated with a passivation layer 17.
    [0008] Each pad 15 is in contact with a last metal level 50 of the interconnection network 19. This level of metal formed under the layer 17 is connected to the remainder of the network by one or more vias 44. FIG. 5B is a sectional view and in perspective of the interposer portion shown in Fig. SA after the steps of: depositing a bias metal layer 52 on the upper face 7 of the interposer; depositing a masking layer 54; 15 etching the masking layer 54 to the layer 52 to form openings 56 facing the studs 15 and to form trenches 58 having flares 60 at their ends, the trenches and their flares being formed at the locations where it is desired to manufacture metallic lines 31 and their flared ends 34; dipping the silicon wafer in which the interposer 3 is formed in an electrolytic bath comprising metal ions; and applying a voltage between an electrode immersed in the electrolytic bath and the bias layer 52 to grow metal lines 31 and connecting elements 13 on this layer 52, respectively in the trenches 58 and in the openings 56. for example, the polarization layer 52 may be a layer or a stack of layers for example of titanium, tungsten, copper or an alloy of these materials, the thickness of the polarization layer may be between 0 , 1 and 1 pin, for example 0.5 pin. The masking layer 54 may be a resin layer whose thickness is chosen greater than the desired thickness of the connection elements 13 and lines 31, for example equal to 100 gm for connecting elements 13 and lines 31 of a height for example 25 pin. Fig. 5C is a sectional and perspective view of the interposer portion shown in Fig. 5B after the steps of: removing the interposer from the electrolytic bath when the lines 31 and the contact members 13 have reached the thickness desired; Removing the masking layer 54, and etching the bias layer 52, the lines 31 and the connecting elements 13 serving as an etching mask. An interposer 3 is obtained whose upper surface 7 carries metal lines 31 arranged between the connection elements 13 electrically connected to the interconnection network 19 via the pads 15. Preferably, metallic lines 32 are formed on the active face 5 of the chip 1 together with the connection elements 9 according to the method described in relation to the figures SA to 5C. Figure 6 is a schematic sectional view taken in the same plane as Figure 2C, this figure illustrating a chip mounted on an interposer. The active face 5 of the chip comprises lines 32 between connection elements 9 and the upper face of the interposer comprises lines 31 between connection elements 13. The assembly of FIG. 6 is obtained after the steps of : arranging an electrically insulating material (WLUF) between the chip and the interposer, around the lines 31 and 32 and 30 of the connecting elements 9 and 13, the material 25 being preferably thermally conductive; depositing an insulating layer 27 on the upper face of the interposer so that the layer covers the chip 1; preferably, polishing the layer 27 so that it is flush with the face of the chip 1 opposite to the active face 5; B13107EN - 12-GR3C0-0471EN01 12 forming openings 62 through the layer 27 to the flares 34 of the lines 31, for example by piercing the layer 27 by means of a laser. The assembly shown in FIGS. 2A, 2B and 2C is then obtained from the assembly of FIG. 6 after the steps of: filling, for example with the squeegee, the openings 62 of a thermally conductive paste, this paste being liquid at room temperature; Hardening the conductive paste to form thermally conductive vias 45; and mount a radiator 29 on the upper face of the assembly. By way of example, the conductive paste is a resin filled with metal flakes cured during a heating step. The resin may be a polymer such as a polyamide. The metallic flakes may be copper flakes. The radiator may be a copper foil adhered to the upper face of the mounting by an adhesive optimized to have a minimum thermal resistance. The silicon wafer in which the interposer is formed is then cut to separate the assembly of the chip 1 on the interposer 3 of the other assemblies formed in and on this wafer. This assembly is then fixed on a support 25 as has been described with reference to Figures LA and 1B. Particular embodiments have been described. Various variations and modifications will be apparent to those skilled in the art. In particular, although an arrangement has been described in which the chip 1 is a thinned chip, it may also be an unthinned chip whose thickness is between 600 and 800 lm. In addition, the components of the chip may be formed in a solid substrate, for example silicon, or in a semiconductor layer of a semiconductor-on-insulator (SOI) type structure.
    [0009] B13107EN - 12-GR3C0-0471EN01 13 In addition, although in the assemblies described above, the chip is mounted on the interposer via micro-pillars, the chip can be mounted on the interposer and electrically connected to the latter by other types of conductive elements, for example metal balls. In each of the assemblies described above, the radiator 29 is a metal sheet bonded to the upper face of the assembly. Other types of radiators may be mounted on the upper face of the assembly, for example a finned radiator. The order of the steps of the manufacturing processes described above may be modified. In addition, steps may be added, modified, or deleted, for example, the planarization step of the layer 27 described in connection with Figure 6 may not be performed. Many variations of such a structure are possible. For example, it can be expected that several chips are mounted on the interposer and that at least one of these chips serves to support at least one other chip. In addition, it can be provided that integrated circuits are formed in and on at least one side of the interposer.
    权利要求:
    Claims (14)
    [0001]
    REVENDICATIONS1. Device comprising: a chip (1) mounted on an interposer (3); an electrically insulating layer (27) coating the upper face (7) of the interposer around the chip; first metal lines (31) resting on the upper face of the interposer and being disposed between conductive elements connecting to the chip (13), at least one end (34) of each first line being disposed beyond the projection of the chip on the interposer; and thermally conductive vias (35) connecting said at least one end to a radiator (29) resting on the upper face of the device.
    [0002]
    2. Device according to claim 1, wherein the conductive connection elements to the chip (13) and the metal lines (31) are in the same first material and have the same thickness.
    [0003]
    3. Device according to claim 1 or 2, wherein the width of each of the first lines (31) is less than the width of said at least one end (34) corresponding.
    [0004]
    4. Device according to claim 2 or 3, wherein the first material is copper.
    [0005]
    5. Device according to any one of claims 1 to 4, wherein each conductive element connecting to the chip (13) is bonded by a solder (23) to a conductive connecting element to the interposer (9) corresponding formed on the chip (1).
    [0006]
    6. Device according to claim 5, wherein second metal lines (32) rest on the chip (1) 30 between said connecting elements to the interposer (9), these second lines (32) being thermally bonded to the first lines (31) by a solder (33).
    [0007]
    7. Device according to claim 6, wherein the connection elements to the interposer (9) and the second metal lines (32) are in the same second material and have the same thickness.
    [0008]
    8. Device according to any one of claims 1 to 7, wherein an electrically insulating material (25) fills the free space between the chip and the interposer.
    [0009]
    9. Device according to claim 8, wherein the second material is copper.
    [0010]
    10. A method of manufacturing a mounting of a chip (1) on an interposer (3), the method comprising the steps of: forming pads (15) on the upper face (7) of the interposer; depositing a metal layer (52) of polarization on the upper face (7) of the interposer; depositing a masking layer (54) on the bias layer (52); etching the masking layer (54) to the polarization layer (52) to form apertures (56) facing the pads and forming trenches (58); immersing the interposer (3) in an electrolytic bath comprising metal ions and applying a voltage between the bias layer (52) and an electrode immersed in the electrolytic bath to grow first metal lines (31) in the trenches (58); ) and chip connection elements (13) in the openings (56); remove the interposer from the electrolytic bath; removing the masking layer (54); etching the bias layer (52), the first metal lines (31) and the chip connecting members (13) serving as an etch mask; mounting the chip (1) on the upper face of the interposer by brazing the connection elements to the chip (13) on connection elements to the interposer (9) carried by the active face (5) of the chip ( 1); B13107EN - 12-GR3C0-0471EN01 16 fill with electrically insulating material (25) the free space between the chip and the interposer; depositing an insulating layer (27) on said upper face (7), the insulating layer (27) flush with the face of the chip (1) opposite the active face (5); and forming thermally conductive vias (45) through the insulating layer (27), these vias being bonded to the ends of the first lines (31).
    [0011]
    11. The method of claim 10, wherein there are provided second metal lines (32) carried by the active face (5) of the chip (1), each second line being thermally bonded to the corresponding first line (31) by a solder (33) made at the step of mounting the chip on the interposer (3). 15
    [0012]
    The method of claim 10 or 11, wherein said trenches (58) comprise flared ends (60).
    [0013]
    13. A method according to any one of claims 10 to 12, further comprising a step of polishing the upper face of the mounting and a step of mounting a radiator (29) on the upper face of the mounting.
    [0014]
    The method of any one of claims 10 to 13, wherein the metal ions of the electrolytic bath are copper ions.
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    法律状态:
    2016-02-19| PLFP| Fee payment|Year of fee payment: 3 |
    2017-02-21| PLFP| Fee payment|Year of fee payment: 4 |
    2018-02-20| PLFP| Fee payment|Year of fee payment: 5 |
    2020-02-20| PLFP| Fee payment|Year of fee payment: 7 |
    2021-02-18| PLFP| Fee payment|Year of fee payment: 8 |
    2022-02-21| PLFP| Fee payment|Year of fee payment: 9 |
    优先权:
    申请号 | 申请日 | 专利标题
    FR1452280A|FR3018953B1|2014-03-19|2014-03-19|INTEGRATED CIRCUIT CHIP MOUNTED ON AN INTERPOSER|FR1452280A| FR3018953B1|2014-03-19|2014-03-19|INTEGRATED CIRCUIT CHIP MOUNTED ON AN INTERPOSER|
    US14/659,680| US9418954B2|2014-03-19|2015-03-17|Integrated circuit chip assembled on an interposer|
    US15/204,488| US9780015B2|2014-03-19|2016-07-07|Integrated circuit chip assembled on an interposer|
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